Towards Nanosheet Field Effect Transistors

The present paper addresses the late development of advanced CMOS technology starting from FinFETs to advanced (3D) technologies such as nanosheet FETs bridged by Gate All Arround GAAFETs. This development is pushed by the More than Moore’s Law as need for rapid, small and low power (new) devices. Gate control has been improved from almost gate to all gate electrostatic control.
GAAFETs are characterized by the better electrostatic and reduced short channel effects, this made GAAFETs the promising devices for next generation of nanoelectronic Integrated Circuits. Hoever, it has been found that the effective channel width (Weff) to layout foot print (LFP) ratio is low causing  smaller ION/IOFF ratio. Moreover, vertical layer stacking increased the parasitic capacitances and hence, drastically affected the device switching characteriscs.

Intorducing nanosheet transistors could eliminbate the GAAFET drawbacks. The main advantage of NS-FETs is their compatibility with other materials like Ge, SiGe and others.

In this work we will make a comparative study between the three FETs (FinFET, GAAFETs and NSFETs). As the NS FETs is considered to be a leading device of the semiconductor device industry in the next years, a simulation study related to its performances is made and basically it has been found that the characteristics are superior compared to other considered devices.

We have achieved simulations on different devices of 7nm gate length and showed that the Nanosheet FET in its different variant will help to stretch the Moore’s Law for the next decades.

For better performance devices, nanofabrication 3D technology still needs more improvements. 3D integration technology is the today and future device and ICs fabrication tools. FinFETs will be gradually replaced by GAAFETs and later on by MBCFETs or NSFETs whicha are supposed to be be key elements in the next two decades. However, improvements in technology itself seem to be crucial.